1. Field of the Invention
The present invention generally relates to processors and methods of controlling processors, and, more particularly, to a processor that executes programmed instructions and a method of controlling such a processor.
2. Description of the Related Art
FIG. 1 shows a first example of a conventional processor having a general register and a floating point register. As shown in FIG. 1, the processor comprises a memory 1, n instruction read unit 3 connected to the memory 1, an instruction execution unit 5 connected to the memory 1 and the instruction read unit 3, a register control unit 7 connected to the instruction execution unit 5, and an interrupt control unit 9 connected to the instruction read unit 3, the instruction execution unit 5, and the register control unit 7.
The instruction read unit 3 includes an instruction read control unit 11, a program counter (PC) 13, and an instruction word register (IR) 15. The instruction read control unit 11 is connected to the memory 1, and the program counter (PC) 13 is connected to the instruction read control unit 11. The instruction word register (IR) 15 is connected to the instruction read control unit 11.
The instruction execution unit 5 includes an instruction decoder unit 17, a load instruction execution unit 19, a store instruction execution unit 21, an instruction execution circuit 23, a gloating point load instruction execution unit 25, a floating point store instruction execution unit 27, and a floating point calculation instruction execution unit 29.
The instruction decoder unit 17 is connected to the instruction word register 15, and the load instruction execution unit 19 is connected to the memory 1 and the instruction decoder unit 17.
The store instruction execution unit 21 is connected to the instruction decoder unit 17 and a general register 37 that will be described later. The instruction execution circuit 23 is connected to the instruction decoder unit 17, the general register 37, and registers 31, 33, and 35 that will be described later. The floating point load instruction execution unit 25 is connected to the memory 1 and the instruction decoder unit 17. The floating point store instruction execution unit 27 and the floating point calculation instruction execution unit 29 are connected to the instruction decoder unit 17 and a floating point register 39 that will be described later.
Meanwhile, the register control unit 7 includes an EPCR register 31, an EPSR register 33, a PSR register 35, the general register 37, and the floating point register 39. The EPCR register 31, the EPSR register 33, and the PSR register 35 are connected to an interrupt control circuit 40. The general register 37 is connected to the load instruction execution unit 19, the store instruction execution unit 21, and the instruction execution circuit 23. The floating point register 39 is connected to the floating point load instruction execution unit 25, the floating point store instruction execution unit 27, and the floating point arithmetic operation instruction execution unit 29.
The interrupt control unit 9 includes the interrupt control circuit 40. The interrupt control circuit 40 is connected to the instruction read control unit 11, the program counter 13, the load instruction execution unit 19, the store instruction execution unit 21, the instruction execution circuit 23, the floating point load instruction execution unit 25, the floating point store instruction execution unit 27, and the floating point arithmetic operation instruction execution unit 29.
In the processor having the above structure, the instruction read unit 3 reads an instruction word indicated by the program counter 13 out of the memory 1, and supplies the instruction word to the instruction execution unit 15 via the instruction word register (IR) 15. If the instruction read control unit 11 receives a branch destination address from the instruction execution unit 5 and the interrupt control circuit 40, which executes an interrupt, the instruction read control unit 11 writes the branch destination address in the program counter 13. In other cases, the instruction read control unit 11 supplies a next instruction word to the instruction execution unit 5, and therefore increments the program counter 13 that indicates the address of the instruction word to be read out. In a case where the instruction read control unit 11 detects an interrupt when reading an instruction word, the instruction read control unit 11 supplies an interrupt signal to the interrupt control circuit 40.
The instruction decoder unit 17 decodes an instruction supplied from the instruction word register 15. In a case of a load instruction, the instruction decoder unit 17 supplies the instruction to the load instruction execution unit 19. In a case of a store instruction, the instruction decoder unit 17 supplies a store instruction to the store instruction execution unit 21. In a case of a floating point load instruction, the instruction decoder unit 17 supplies the instruction to the floating point load instruction execution unit 25. In a case of a floating point store instruction, the instruction decoder unit 17 supplies the instruction to the floating point store instruction execution unit 27. In a case of a floating point calculating instruction, the instruction decoder unit 17 supplies the instruction to the floating point calculating instruction execution unit 29. In a case of an interrupt return instruction to any other instruction, the instruction decoder unit 17 supplies the instruction to the instruction execution circuit 23.
When the load instruction execution unit 19 receives the load instruction, the load instruction execution unit 19 reads data from a region in the memory 1 corresponding to an effective address determined based on a value read out from the general register 37, and writes the result in the general register 37, as shown in FIG. 2. Here, the load instruction includes an instruction code OP-CODE, and codes GR1, GR2, and GRD for designating a register. The addition result of the register value indicated by the code GR1 and the register value indicated by the code GR2 represents the address of the data to be loaded, and the code GRD indicates the number of a register that holds the addition result. However, in a case where the load instruction execution unit 19 detects an interrupt when executing the load instruction, the load instruction execution unit supplies an interrupt signal to the interrupt control circuit 40.
Likewise, when the store instruction execution unit 21 receives the store instruction, the store instruction execution unit 21 reads data from the region in the general register 37 corresponding to an effective address determined based on a value read out from the general register, and writes the result in the region of the memory 1 corresponding to the effective address, as shown in FIG. 4. Here, the store instruction includes an instruction code OP-CODE, and codes GR1, GR2, and GRS for designating a register. The addition result of the register value indicated by the code GR1 and the register value indicated by the code GR2 represents the address of data to be stored, and the code GRS indicates the number of a register that holds a value to be written. However, in a case the store instruction execution unit 21 detects an interrupt when executing the store instruction, the store instruction execution unit 21 supplies an interrupt signal to the interrupt control circuit 40.
When the floating point load instruction execution unit 25 receives the floating point load instruction, the floating point load instruction execution unit 25 reads data from the region in the memory 1 corresponding to an effective address determined based on a value read out from the general register 37, and writes the result in the floating point register 39. However, in a case where the floating point load instruction execution unit 25 detects an interrupt when executing the floating point load instruction, the floating point load instruction execution unit 25 supplies an interrupt signal to the interrupt control circuit 40.
When the floating point store instruction execution unit 27 receives the floating point store instruction, the floating point store instruction execution unit 27 reads data from the region in the floating point register 39 corresponding to an effective address determined based on a value read out from the general register 37, and writes the result in the region memory 1 corresponding to the effective address. However, in a case where the floating point store instruction execution unit 27 detects an interrupt while executing the floating point store instruction, the floating point store instruction execution unit 27 supplies an interrupt signal to the interrupt control circuit 40.
The floating point arithmetic operation instruction execution unit 29 executes an operation based on a value read out from the floating point register 39 when the floating point arithmetic operation instruction is supplied. The floating point arithmetic operation instruction execution unit 29 then writes the result in the floating point register 39.
When the instruction execution circuit 23 receives an arithmetic operation instruction from the instruction decoder unit 17, the instruction execution circuit 23 performs an operation based on a value read out from the general register 37, and writes the result in the general register 37. In a case where the instruction execution circuit 23 receives a branch instruction from the instruction decoder unit 17, the instruction execution circuit 23 supplies the branch destination address to the program counter 13 at the time of the occurrence of the branch. In a case where the instruction execution circuit 23 receives an interrupt return instruction, the instruction execution circuit 23 writes data that represents the pre-interrupt operation state in the register PSR 35. The instruction execution circuit 23 then reads the address of the instruction at the return destination from the register EPCR 31, and supplies the address as the branch destination address to the program counter 13. However, if the instruction execution circuit 23 detects an interrupt while executing the above instruction, the instruction execution circuit 23 supplies an interrupt signal to the interrupt control circuit 40.
The register EPCR 31 holds the address of an instruction corresponding to the return destination from the interrupt. The address is set at the occurrence of the interrupt. The register PSR 35 holds data that represents the operation state, and the register EPSR 33 holds data that represents the pre-interrupt operation state set prior to the occurrence of the interrupt.
Based on the interrupt signal supplied from the instruction read unit 3 or the instruction execution unit 5, the interrupt control circuit 40 writes the instruction address corresponding to the interrupt return destination in the register EPCR 31, the data that represents the pre-interrupt operation state in the register EPSR 33, and the operation state corresponding to the interrupt in the PSR 35. The interrupt control circuit 40 supplies the branch destination address corresponding to the interrupt to the instruction read unit 3.
In the following, the operations of the above processor will be summarized. The operation of the processor in the initial stage is as follows. The instruction read unit 3 reads out an instruction word indicated by the program counter 13, supplies the instruction word to the instruction execution unit 5, and then executes the supplied instruction.
When an interrupt occurs, the interrupt control circuit 40 writes the instruction address corresponding to the interrupt return destination in the register EPCR 31, the data that represents the pre-interrupt operation state in the EPSR 33, and the operation state of the interrupt in the PSR 35, based on the interrupt signal supplied from the instruction read unit 3 or the instruction execution unit 5. Also, the interrupt control circuit 40 supplies the branch destination address corresponding to the interrupt to the instruction read unit 3. The instruction read unit 3 then reads out an instruction word in accordance with the branch destination address supplied from the interrupt control unit 9, and supplies the instruction word to the instruction execution unit 5. After that, the operation is carried out in the same manner as in the normal state described above.
At the time of interrupt return, the instruction execution unit 5 executes an interrupt return instruction, thereby writing the value of the register EPSR 33 in the register PSR 35. The instruction execution unit 5 reads out the data from the register EPCR 31, and supplies the result as the branch destination address to the instruction read unit 3. The instruction read unit 3 in turn reads out an instruction word in accordance with the branch destination address supplied from the instruction execution unit 5, and supplies the instruction word to the instruction execution unit 5. After that, the operation is performed in the same manner as in the above-described normal state.
FIG. 6 shows a second example of the conventional processor having a general register and a floating point register. This processor has the same structure as the processor of the first example, except that an instruction execution unit 6 further comprises an arithmetic operation instruction execution unit 22, and a register control unit 8 further comprises a condition register 30. In FIG. 6, the same components as in FIG. 1 are denoted by the same reference numerals, and explanations for them are omitted in this description.
When receiving an arithmetic instruction, the arithmetic operation instruction execution unit 22 reads out data from the region in the general register 37 corresponding to an effective address determined based on a value read out from the general register 37, and performs an arithmetic operation based on the read data. The result of the arithmetic operation is then written in the general register 37, as shown in FIG. 7. The arithmetic operation instruction has the same format as the load instruction shown in FIG. 3. When receiving a comparison instruction, the arithmetic operation instruction execution unit 22 compares two values read out from the general register 37. If the two values are equal, the arithmetic operation instruction execution unit 22 writes the data indicating truth in the condition register 30. If the two values are not equal, the arithmetic operation instruction execution unit 22 writes data indicating false in the condition register 30.
FIG. 8 shows a third example of the conventional processor. In FIG. 8, the same components as in FIG. 6 are denoted by the same reference numerals, and explanations for them are omitted in this description. As shown in FIG. 8, this processor comprises the memory 1, an instruction read unit 303 connected to the memory 1, an instruction execution unit 307 connected to the memory 1 and the instruction read unit 303, a register control unit 309 connected to the instruction execution unit 307, and the interrupt control unit 9 connected to the instruction read unit 303, the instruction execution unit 307, and the register control unit 309.
The instruction read unit 303 comprises the instruction read control unit 11, the program counter 13 the instruction word register 15, and an instruction break detector unit 301. The instruction break detector unit 301 is connected to the memory 1 and the instruction execution circuit 23.
The instruction execution unit 307 comprises the instruction decoder unit 17, the load instruction execution unit 19, the store instruction execution unit 21, the arithmetic operation instruction execution unit 22, the instruction execution circuit 23, and a data break detector unit 305. The data break detector unit 305 is connected to the load instruction execution unit 19, the store instruction execution unit 21, and the instruction execution circuit 23.
The interrupt control circuit 40 is connected to the instruction read control unit 11, the program counter 13, the instruction break detector unit 301, the load instruction execution unit 19, the store instruction execution unit 21, the arithmetic operation instruction execution unit 22, the instruction execution circuit 23, and the data break detector unit 305.
When receiving a break point instruction from the instruction decoder unit 17, the instruction execution circuit 23 notifies the interrupt control circuit 40 of the software break. When receiving an instruction break point register read instruction from the instruction decoder unit 17, the instruction execution circuit 23 reads a break point object address from an instruction break point register in the instruction break detector unit 301, and writes the read address in the general register 37. When receiving an instruction break point register write instruction from the instruction decoder unit 17, the instruction execution circuit 23 writes the break point object address corresponding to a value read out from the general register 37 into the instruction break point register in the instruction break detector break detector unit 301.
Likewise, when receiving a data break point register read instruction from the instruction decoder unit 17, the instruction execution circuit 23 reads out a break point object address from a data break point register in the data break detector unit 305, and writes the read address into the general register 37. When receiving a data break point register write instruction from the instruction decoder unit 17, the instruction execution circuit 23 writes the break point object address corresponding to a value read out from the general register 37 into the data break point register in the data break detector unit 305.
FIG. 9 shows the structure of the instruction break detector unit 301. As shown in FIG. 9, the instruction break detector 301 comprises detectors 311 to 314, address fields 315 to 318, E fields 319 to 322, V fields 323 to 326, and an OR circuit 327.
The address fields 315 to 318 each hold a break point object address, and constitute the above-mentioned instruction break point register. The E fields 319 to 322 each holds data that indicates whether or not an instruction break operation is valid. More specifically, when the instruction break operation is invalid, the corresponding one of the E fields 319 to 322 holds the value “0”. When the instruction break operation is valid, the corresponding one of the E fields 319 to 322 holds the value “1”. The E fields 319 to 322 constitute the above-mentioned instruction break point register. The V fields 323 to 326 each hold data that indicates whether or not an instruction break has been detected. More specifically, if no instruction break has been detected, the corresponding one of the V fields 323 to 326 holds the value “0”. If an instruction break has been detected, the corresponding one of the V fields 323 to 326 holds the value “1”.
The detectors 311 to 314 each determine whether or not an instruction break is established. More specifically, each of the detectors 311 to 314 compares an instruction address supplied from the memory 1 with an address supplied from the instruction break point register. If the two addresses coincide with each other, the value “1” is written in the corresponding one of the V fields 323 to 326, and a match signal mt is supplied to the OR circuit 327. An interrupt signal is then transmitted form the OR circuit 327 to the interrupt control circuit 40, thereby notifying the interrupt control circuit 40 of the instruction break.
FIG. 10 shows the structure of the data break detector unit 305. As shown in FIG. 10, the data break detector unit 305 also comprises the detectors 311 to 314, the address fields 315 to 318, the E fields 319 to 322, the V fields 323 to 326, and the OR circuit 327.
The address fields 315 to 318 each hold a break point object address, and constitute the above-mentioned data break point register. The E fields 319 to 322 each hold data that indicates whether or not a data break operation is valid. More specifically, if the data break operation is invalid, the corresponding one of the E fields 319 to 322 holds the value “1”. If the data break operation is valid, the corresponding one of the E fields 319 to 322 holds the value “0”. The E fields 319 to 322 constitute the data break point register. The V fields 323 to 326 each hold data that indicates whether or not a data break has been detected. More specifically, when no data break has been detected, the corresponding one of the V fields 323 to 326 holds the value “0”. When a data break has been detected, the corresponding one of the V fields 323 to 326 holds the value “1”.
The detectors 311 to 314 each determine whether or not a data break is established. More specifically, the detectors 311 to 314 each compare an effective address (data address of a load store instruction supplied form the memory 1 with a break point object address stored in the corresponding one of the address fields 315 to 318. When the two addresses coincides with each other, “1” is written in the corresponding one of the V fields 323 to 326, and a match signal mt is supplied to the OR circuit 327. By doing so, an interrupt signal is supplied from the OR circuit 327 to the interrupt control circuit 40, thereby notifying the interrupt control circuit 40 of the data break.
FIG. 11 is a flowchart showing a data break interrupt operation of the above processor by an interrupt operation program. As shown in FIG. 11, a context is saved in step S1, and a data break operation is performed in step S2. The context is then restored in step S3, and an interrupt return instruction is executed so as to return from the interrupt operation in step S4. The interrupt operation then comes to an end.
FIG. 12 is a flowchart showing a software break interrupt operation by the interrupt operation program. As shown in FIG. 12, a context is saved in step S1, and a software break operation is performed in step S2. The context is restored in step S3, and an interrupt return instruction is executed so as to return from the interrupt operation in step S4. The interrupt operation then comes to an end.
In the above conventional processors, a control method of simultaneously executing a plurality of instructions, such as a superscalar technique or a speculative execution technique, is employed to improve the performance of the processor, utilizing the parallelism of instruction words that constitute a program. Generally, such a processor comprises a plurality of instruction execution units, and sequentially executes the instructions contained in the program. A plurality of instructions can be read out from the memory in one cycle, and a plurality of instructions can be issued in one cycle, with the dependency among the instructions being taken into account.
In the instruction execution control, an out-of-order completion technique is employed to increase the performance at the instruction level of the processor. Here, the “out-of-order completion” indicates that the issuance order of instructions on the program differs from the instruction execution order, i.e., the instruction completion order. By performing such an execution control operation, the effective availability of the instruction execution unit is increased, and the entire execution time of the program is shortened. To ensure the instruction order at the time of the generation of the program, the data dependency relationship or the control dependency relationship needs to be taken into consideration. The information on the dependency relationship is extracted from the information written in the instruction words.
In a load operation performed on the memory 1, data is read out from the memory 1, and the result is written in the register in the processor. After that, a series of operations depending on the read data are started. Accordingly, a load operation from the memory 1 is started so as to reduce adverse influence onto the operation of the entire processor from a delay of access to the memory 1 caused by cache miss or the like.
From the above reasons, when a program is generated, a load instruction may be placed in a further front position in the program so as to start the load operation in an earlier stage. In this arrangement, the same effects as obtained by moving the load instruction on the program can be obtained. If the load operation is executed prior to the store operation in the memory 1, data processing is performed in the same execution sequence as long as the address regions of the data in both operations do not overlap with each other. However, even if the address regions only partially overlap with each other, there will be a difference in the data process results.
More specifically, when the load operation is performed prior to the store operation, the previous data stored prior to the store operation is read out by the load operation, through the store data stored in the memory 1 by the store operation should be read out by the load operation. With the change in the execution sequence, the data processing operation changes accordingly. This problem is known as the problem of ambiguous memory reference. In the prior art, to avoid this problem, a load operation cannot be performed on the memory 1 prior to a store operation on the memory 1.
Meanwhile, a technique of moving instructions beyond the boundaries between basic blocks by a compiler is known as the wide area instruction movement technique. Further, instruction movement beyond condition branching in the wide area instruction movement is known as the speculative instruction movement technique. However, when an exception occurs with a speculatively moved instruction, the ability to perform an exception operation drastically deteriorates, or an unexpected break occurs in the program execution despite the originally programmed sequence.
For instance, when an instruction that has a possibility of causing a page fault with necessary data missing from the memory is speculatively moved, an exception operation program that causes a page fault at the movement destination is executed, resulting in a drop in the operation ability. If a division instruction is speculatively moved, a zero division operation might be carried out at the movement destination, but the execution of the program is stopped in such a case. An exception caused by the execution of a speculatively moved instruction is called a “speculative exception”.
As a means to solve the above problems, a method of delaying the occurrence of a speculative exception using a non-exception instruction is known. A non-exception method in which a speculative exception operation is delayed is mentioned in the reference “A VLIW Architecture for a Trace Scheduling Compiler, Proceedings of the 2nd International Conference on Architectural Support for Programming Languages and Operating Systems, pp. 180-192, 1987 (B. P. Colwel, B. P. Nix, J. J. O'Donnel, D. B. Papworth, and P. K. Rodman)”. Meanwhile, a method of scheduling the restart of execution from a speculative exception is mentioned in the reference “Sentinel Scheduling for VLIW and Superscalar Processor, Proceedings of the Fifth International Conference on Architectural Support for Programming Languages and Operating Systems, pp. 238-247, 1992 (S. A. Mahlke, W. Y. Chen, W. W. Hwu, B. R. Rau, and M. S. Schlansker)”.
There are two types of exceptions: one is an exception with which the main operation can be continued by canceling the exception factor, like a page fault; and the other one is an exception with which the main operation cannot be continued, like a zero division operation. In the data processing operation using the non-exception instruction, each exception is detected as a speculative exception, and executed after a predetermined period of time.
However, since an exception operation that can be continued and the following main operation are performed by executing an interrupt operation program, the program becomes too long as a whole. As a result, the capacity required for the processor becomes too large, and the operation speed drops accordingly.
Furthermore, when a program including the non-exception instruction is being debugged, there is another problem that the execution of the program is interrupted by a data break with an instruction not ensured in the original execution sequence among speculatively moved instructions.